Shantanu Mishra

Experience

Advanced Micro Devices
Sr. Software Engineer, Hyderabad
Dec 2022 - present

As part of AIG (Artificial Intelligence Group), implemented faster functionally-accurate simulation flow by leveraging a compiler-based approach to generate a functional core which replaces the cycle-accurate core while maintaining register information throughout the AI inference cluster.
Achieved a significant milestone with over 100x speedup (days to minutes) in simulating ML networks on AI inference accelerators, thereby speeding the iteration cycles for developers working on the FlexML compiler.

Software Engineer II, Hyderabad
Feb 2022 - Nov 2022

Developed a multi-threaded cycle-accurate simulation framework which enabled parallel execution of models while presenting a unified single-threaded application interface for simulation developers.
Created a cycle-accurate model of AI inference engines on this framework, achieving scalable performance enhancements with increased thread counts and design complexities, yielding a 5-10x speedup compared to traditional SystemC models.
Improved simulation accuracy and efficiency through model optimizations and added many features enabling debugging capabilities like selective VCD, zero-latency fast paths, etc., for the simulation model.

Xilinx
Software Engineer II, Hyderabad
Nov 2021 - Feb 2022

Developed a transaction-accurate simulation flow with a speedup of 10-100x while simulating HLS designs.

Software Engineer I, Hyderabad
Aug 2020 - Sept 2021

Developed SystemC models of IPs such as AXI Interrupt Controller, Clocking Wizard, and AXI Mailbox as part of the SW Emulation and Acceleration team.
Created rigorous UVM test benches and modules for verifying mentioned IPs.

Intel
Undergraduate Intern, Bangalore
Jul 2019 - Jun 2020

Developed the PCIe driver for enabling the hardware subsystem responsible for queue management in server SoCs.
Enabled virtualization modes like Single-root IOV and Scalable IOV and interfaced user and test apps with the kernel module through IOCTL and sysfs for testing the subsystem’s capabilities like FLR, MSI, and IOV.
Designed DMA APIs to dynamically allocate and map memory in NUMA-based systems.
Conducted multiple hands-on training sessions on Linux Kernel Modules and PCIe Device Drivers.

AerospaceResearch.net
Open Source Developer, Google Summer of Code
May 2018 - Aug 2019

Developer and maintainer of VisMa and contributor to DirectDemod.
Added CI, webhooks, and bots for automating workflow, code review, and unit-testing.
Mentored and helped beginner developers delve into the world of OSS during GSoC’19.

Hindustan Aeronautics Ltd - Aerospace Division
Summer Intern, Bangalore
May 2017 - Jul 2017

Collaborated with the team working on the electronic systems of L-40 strap-on boosters of GSLV Mk II.
Learned about the control systems based on the Strap-down Inertial Navigation system used in the third stage of GSLV.
Produced a project report on the potential of harnessing solar energy at HAL.

CytoCube
Dept of Instrumentation & Applied Physics, IISc
Apr 2019 - June 2019

Created control software for the prototype of CytoCube - a cost-effective, fast, and efficient flow cytometer.
Integrated XIMEA cameras, optimized the code for camera and motor-axis movements increasing the speedup of blood scans by 5x, and assisted in PCB design.
Automated the device setup flow, which previously required an equipment assistant to calibrate and setup the device.
Trained an FRCNN-based model to identify various blood cell types and get the blood count using OpenCV.

5-stage Pipelined MIPS Processor
BITS Hyderabad
Mar 2019 - Apr 2019

Designed a 32-bit 5-stage pipelined processor with forwarding and branch prediction supporting 20 different instructions (R-type, I-type, Jump/Branch) based on RISC ISA.
Scripted a simple assembler in Python to generate bitstream for the instructions and implemented on the Spartan-3 FPGA board.

Performance Optimization of MPI Parallel Code in FreeFlow
BITS Hyderabad
Aug 2018 - Nov 2018

Optimized code for mesh-free fluid-dynamics equation solvers using OpenMP and OpenACC pragmas to support hybrid parallelization along with MPI.
Profiled the source code using Valgrind to detect memory leaks and PETSc to improve performance on parallel processors.

VISual MAth
Google Summer of Code ‘18
May 2018 - Aug 2018

Developed a math equation solver and visualizer using Python with AerospaceResearch.net.
Enhanced the GUI, added interactive graph plots, and added unit tests using pytest.
Modified the codebase to follow the object-oriented style and created modules for functions, simplifier, calculus, solvers, and matrix.

Operational Feasibility of Solar Power
Hindustan Aeronautics Ltd
May 2017 - Jul 2017

Completed a report on the Usage of Sustainable Renewable Resources.
The report expands on the various solar technologies available and how to integrate and optimize them to power machinery and facilities at HAL.

LLVM-Based Core Model for Functional Simulation of the AI Engine
2024 (pending)
A Multi-Threaded Simulator Framework for Cycle-Accurate Performance Modeling
2022
Compiler-Based Generation of Transaction Accurate Models from High-Level Languages
2021

World Quant University
2020-2022

Birla Institute of Technology and Science
2015-2020

Excel Junior College
2013-2015

Brahma Prakash DAV School
2013